Automated or automatic test systems are widely used by manufacturers in the electronic industry to test various devices, including electronic components and integrated circuits (ICs), to cull defective devices before they are incorporated in products. Broadly, there are three types of digital devices that are commonly tested using automated test systems, those having memory arrays or circuits, such as flash memory or random access memories (RAM), those having logic circuits, such as processors, application specific ICs (ASICs) and programmable logic devices (PLDs), and those having both memory circuits and logic circuits. Generally, it is desirable to test the devices at several points during the manufacturing process, including while they are still part of a wafer or substrate, after dicing but before they are packaged, and after packaging the devices but before they are mounted or assembled on modules, cards or boards. This repetitive testing imposes demands on automated test systems to perform tests at high speed and with a high degree of accuracy. Moreover, the trend in the electronics industry has been to further increase the miniaturization of electronic devices and circuits, thereby allowing for an increase in the complexity of the devices. As the devices become more complex, the complexity of the test systems and their cost increase correspondingly.
FIG. 1 illustrates an exemplary part of a conventional test system 10 for testing a device, commonly known as a Device Under Test or DUT 12, having a number of pins 14. Referring to FIG. 1, the test system 10 typically includes a general purpose computer 16 or personal computer (PC), a clock 18, a memory and sequencer 20 having a pattern memory and sequencing circuit, a number of timing and format circuits (T/Fs 22), and a number of pin electronics or PE channels 24. Generally, the test system 10 includes one T/F 22 and an associated P/E channel 24 for each pin 14 on the DUT 12, shown here as having pins 1 through n. The computer 16 loads test signals or patterns, commonly known as test vectors, into the memory and sequencer 20 and controls operation of other components of the test system 10. The clock 18 has a clock cycle and generates system clocks or clock signals and the test system period, both of which are provided to the memory and sequencer 20, the T/Fs 22, and other pipeline circuits in the test system 10. The memory and sequencer 20 stores and sequences test vectors used during the testing process. Commonly, the memory of the memory and sequencer 20 is either logic vector memory (LVM) which stores logic vectors, scan memory, which store scan vectors, or both. The T/Fs 22 adjust the timing and formatting of various signals of the test vectors, i.e., data, strobe and input/output (I/O) control signals, received from the memory and sequencer 20 and couple the output from the memory and sequencer to the DUT 12, through PE channels 24.
Each PE channel 24 typically includes a PE driver 26 for applying a test vector or data, to a pin 14 of the DUT 12, a comparator 28 for comparing a signal output from the DUT with an expected output signal, and an error logic circuit 30 for coupling results of the comparison back to error processing circuitry and an error capture memory (not shown). Generally, the PE driver 26 and the comparator 28 are not active in the same PE channels 24 at the same time, since pin 14 is either receiving data or control signals or transmitting a result at a given time. The PE channels 24 further include a data line 32 for coupling the test vectors from the T/F 22 to the PE driver 26 and to the error logic 30, an enable or control line 34 for enabling the PE driver to apply the test vector to the DUT 12, and a strobe line 36 for enabling the error logic 30.
A fundamental problem with the above test system 10 is that LVM and scan memory are typically expensive resources in automatic test systems. Moreover, conventional test systems typically only have a limited depth or amount of LVM available on each PE channel or pin on the DUT and, if available, a fixed width scan memory also having a limited depth dedicated to a fixed number of the PE channels or pins. The depth of these memories is important because as DUTs grow in density they require more and larger test vectors using more pattern memory.
Another problem with the above test system 10, related to the above problem, is its inability to vary the widths and depths of the LVM and scan memories without extensive re-wiring of the hardwiring of connection between the memory and sequencer 20 and the PE channels. Furthermore, this inability to vary the widths and depths of the LVM and scan memories results in inefficiency in the utilization of test system resources. That is, conventional test system 10 cannot vary the ratio of width to depth, the aspect ratio, of available pattern memory. For example, in a test system 10 designed to accommodate 64 pin devices, LVM outputs maybe mapped to 32 of the available PE channels to accommodate a 32-bit wide test vector. However, the depth or size of the test vector will be limited by the depth or size of the LVM. Moreover, even if the test system 10 is used to test a device having fewer than 64 pins and requiring only 16-bit wide test vectors, the unused portion of the LVM corresponding to the unused LVM outputs cannot be used to increase the memory available for the 16-bit wide test vectors.
Yet another problem with the test system 10 described above, is the inability to route any output from the memory and sequencer 20 to any PE channel 24, and therefore to any pin 14 on the DUT 12, limiting the flexibility and pattern memory depth when parallel testing multiple DUTs on a test site.
Still another problem with the conventional test system 10 described above is its inability to clock or change the test pattern applied to a DUT 12 at a rate greater than once in a clock-cycle.
Accordingly, there is a need for a test system and method of using the same that increases the efficiency and utilization of test system resources by maximizing the available storage space in pattern memory for a test vector of a given width. There is a further need for a system and method that enables the aspect ratio of available pattern memory to be tailored based on a width of required test vectors. There is yet a further need for a system and method capable of routing any output from the pattern memory to any PE channel. There is a still further need for a system and method capable of changing the test vector applied from any output from the pattern memory to any PE channel at a rate greater than once in a clock cycle.
The system and method of the present invention provides these and other advantages over the prior art.